Chern networks: reconciling fundamental physics and device engineering (2025)

An uncontroversial observation concerning the trajectory of topological condensed matter research, is that the bifurcation into fundamental and applied categories has been accelerating^1,2. The previous acknowledgment of applications in publications has been a slight reference to a specific use case at the end of the abstract and a second time in the concluding statements. This has been replaced by detailed and precise demonstrations of topological phenomena, with the specific intention of investigating the potential role of topological matter in future device technologies. Perhaps one of the most recent and elegant demonstrations of such applied topological research comes in the form of Chern networks^3,4,5,6. Generally speaking, a Chern network, as shown schematically in Fig.1, refers to the electrical and/or magnetic control of dissipation-free 1D chiral edge state propagation between non-local electrical contacts within a heterogeneous device design. To be clear, the definition of the quantum anomalous Hall (QAH) effect is a state in which the longitudinal resistivity disappears, ρ_xx = 0, while at the same time the Hall resistivity becomes exactly quantized as ρ_xy = h/e² in the absence of a net magnetic flux penetrating the device structure^7,8. By controlling the sign of the applied perpendicular magnetic field, or ultimately an applied electric field as illustrated in Fig.1(A), the chirality of the edge state may be controlled. The roots of 1D chiral edge transport in the presence of broken time-reversal symmetry may be traced directly back to the foundational work by Haldane⁹. Nevertheless, the functional physical principle behind Chern networks is the successful exploitation of the bulk–boundary correspondence between fabricated device regions that possess any discrepancy between regional (first) Chern numbers. Therefore, the idea of being able to use applied electromagnetic fields to alter the direction and destination of dissipationless edge current flow provokes images of a clear topological means to guide the transmission of information within interconnected and arbitrarily complex device geometries, as shown in Fig.1B. In a short amount of time, the evolutionary arc that connects the early efforts in the fabrication of a Chern network using antiferromagnetic MnBi₂Te₄ layers grown via molecular beam epitaxy (MBE) immersed within a strong, but non-quantizing, magnetic field³ to the most recent use of magnetically-doped topological insulators created via an in-situ MBE mask that function without the need for continuous application of an external magnetic field⁶, it is clear that continued refinement of Chern networks will produce quantized topological transmission of current between non-locally connected contacts. While the continued improvement of Chern networks may be a forgone conclusion, the more pertinent questions, asked from a more applied perspective, are two-fold: (1) what device need is being addressed? (2) how does the successful implementation of the Chern network compare with other proposed device engineering solutions? Questions about the form of future electronic device technologies have been a topic of heavy debate for many years. To be more specific, the most quoted proposed solution that Chern networks are cited to address is the issue of power consumption. Currently, traditional electronic information processing is accomplished using highly interconnected complementary metal-oxide-semiconductor (CMOS) device technologies. It is well-known that within CMOS, most of the power input to a chip is consumed when the state of the device is being altered either from the “off" state to “on" state or vice versa. Given the sheer number of power dissipating transistors that comprise current microelectronic chip designs—134 billion in the Apple M2 Ultra¹⁰—it is unsurprising that even the most energy efficient device solutions will dissipate a significant amount of energy in the course of normal operation. To this end, the semiconductor industry, and device engineers more broadly, are keenly aware of the power dissipation issue and have actively sought alternative “Beyond CMOS" device technologies using new physical principles and materials. If, indeed, the Chern network or another forthcoming solution proposes a device for practical consideration then there exist well-established device metrics that may be found in the International Roadmap of Devices and Systems (IDRS) against which these proposed devices must be benchmarked^11,12,13. In this Comment, I point to some of the issues related to size, temperature, and performance that may hinder Chern networks as a viable technological solution by device engineers, and I ask questions that require the attention of both physics and engineering researchers. In doing so, my goal is to take one step towards normalizing and applying the relevant figures of merit, where appropriate, to prod the nascent dialog between condensed matter physics and device engineering towards joint solutions that address real-life performance needs.

From an engineering perspective, temperature is a vital quantity. Naturally, if the intended application is to be within the context of, for example, superconducting electronics¹⁵, then the energy scales of the system are expected to be small and, therefore, a path to functionality at room temperature, here defined to be T_RT = 300 K, need not exist. However, if conventional computing, memory or spintronic applications are the goal, then there must necessarily be a path—regardless of the circuitry—that ends with room-temperature operation. To date, there are two separate paths that have been explored as a means to implement the QAH effect within topological materials. The first and most successful approach is to use magnetic dopants to fabricate compounds such as Cr-doped (BiSb)₂Te₃ or V-doped (BiSb)₂Te₃^6,16,17. Indeed, such material systems have demonstrated the QAH effect, albeit with two caveats. First, the observation of the QAH effect is at very low temperatures, typically below T ≤ 200 mK despite observed Curie temperatures that are on the order of T_C ≈ 20K¹⁷. The second caveat is that the longitudinal resistance ρ_xx ≈ 0 only at the lowest system temperatures and in the presence of the smallest excitation currents. The difficulty in obtaining quantized transport in magnetically doped topological materials indicates that the magnetic exchange gap, Δ_EX, that is opened by the ferromagnetic orientation of the dopant ions is very small compared to the system thermal energy^18,19. Furthermore, the non-quantized transport at the edge of the system dictates that the system is not topological and indicates the existence of an alternative conduction path via the bulk^16,17.

Nevertheless, opportunities exist to make progress towards greater thermal stability in Chern networks. Rather than appealing to an overall ferromagnetic state mediated by magnetic dopants, an alternative that may lead to higher resilience to thermal effects may be proximity-induced magnetism. From a naive perspective, the existence of a multitude of magnetic materials boasting Curie temperatures that are greater than T_RT and topological materials that host topological phases at temperatures greater than T_RT accommodates the possibility of engineering a high-temperature QAH insulator phase^20,21. To this end, there have been a number of significant studies that have paired magnetic materials with high Curie temperatures and topological materials^21,22,23,24. At this time, however, while there are clear signatures of induced magnetism in the target topological material, there is no clear evidence of a Chern insulator produced via proximity coupling of disparate magnetic and topological materials. Yet one of the most compelling implications resulting from the experimental and subsequent theoretical work²⁵ is that the presence of an overall long-range magnetic phase—either ferromagnetic or antiferromagnetic—may be irrelevant to the ability to instill high-temperature proximity-coupled phases within an adjacent topological material. In this context, if high-temperature operation is to be optimized, then the choice of magnetic materials should not be predicated on the energy scale associated with T_C but rather based on two criteria: (1) the median physical distance between the magnetic atoms within the host magnetic material and the surface of the topological material, and (2) the magnitude of the magnetic moment associated with the magnetic atoms in the host magnetic material.

When considering applied topology from both the condensed matter and device engineering perspectives, there is no larger separation between the disciplines as when considering the performance expectation gap between condensed matter perception and device engineering reality. Within condensed matter physics literature, the Chern network is a virtual panacea that is poised to cure the real engineering problems surrounding the reduced performance enhancements obtained by the inexorable shrinking of CMOS implementations of semiconductor logic devices. However, the performance degradation obtained with device scaling is well understood by the device engineering community and routinely updates the metrics by which they measure the performance of semiconductor logic and the constituent devices¹². Furthermore, device engineering has recognized the need to find disruptive technologies that will enhance the performance of key components of digital information processing¹¹. Thus, any proffered solution must be benchmarked against current CMOS on these key figures of merit (FoM). For instance, the use of topological materials, and even Chern networks, has long been proposed as a methodology to overcome the rise in the resistance of copper interconnects with continued scaling due to grain boundary and surface scattering¹². Benchmarking the use of topological materials as interconnects has, indeed, shown benefits over copper with the caveat being that such topological benefits only become appreciable when the interconnect diameters are scaled below 6nm in width and ignores the question of how one would integrate these interconnects into the CMOS fabrication process to replace Cu²⁶. In light of this, we apply basic benchmarking to the Chern network to determine where, as of now, this scientific development sits amongst other current and proposed technologies on two key FoM: subthreshold slope and drive current. Thus, to make a comparison between the Chern network performance and the 2022 generation, or 3nm-node logic device specifications, we use an analogy with the edge channel current to represent the drain current, I_DS, with the backgate voltage being the same as the gate-to-source voltage, V_GS.

Subthreshold slope

We begin with the subthreshold slope (S_sub), which is a FoM that quantifies the amount of power that is required to change the current flow by one order of magnitude:

Subthreshold slope is one of the primary measures for overall comparison of effectiveness of current modulation via an external applied electric field. For a standard CMOS transistor, the subthreshold slope is limited by thermionic emission of carriers over the potential barrier that separates the origin of carriers within a transistor, i.e., the source, from the point where the injected carriers are extracted, i.e., the drain. The fundamental limit for CMOS transistors is S_sub = 60 mV/dec and state of the art transistors operate very close to this fundamental limit at between S_sub = 75 –82 mV/dec in the 2022 production line¹².

A simple calculation using published data indicates that the Chern network, currently, has a subthreshold slope of S_sub = 333.45 mV/dec⁵. While the calculated S_sub may be improved over successive iterations, the major difficulty is that these measurements are carried out at 20 mK and not at room temperature. Further, the voltages that are applied to the gate to modulate the conduction are several orders of magnitude larger than in the state-of-the-art CMOS transistor. However, the expressly low temperature operation may be advantageous in certain applications due to the inability of CMOS devices to operate at low temperatures due to dopant freeze-out—or the state where the thermal energy imparted to the dopant atoms is insufficient for them to become ionized. Therefore, Chern networks may find utilization in applications such as superconducting spintronics for alternative forms of low-temperature logic^27,28.

Drive Current

The reality of the highly interconnected architecture of CMOS is that the successful operation of one isolated device is of questionable value. While such singular demonstrations are important as a means of determining basic proof of concept, it is crucial to ensure that a path exists for one singular device concept to be capable of producing sufficient current to drive subsequent stages of device architecture. In logic core devices produced for the 20223nm technology node, the main MOS architecture is the FinFET, which consists of a thin Si nanoribbon that is surrounded on three sides by a metal gate¹². Therefore, when the device is turned on by inverting the surface beneath the gate, three conductive channels are produced resulting in an on-state current of between I_on = 65–88 μA per device with a corresponding off-state current of I_off = 0.1–10 nA/μm¹². Given the topological nature of the current flow in the Chern network, it is natural to expect the Hall current to be quantized. Using the same topological argument, the longitudinal current may flow without dissipation, however, there is an associated active device resistance that is fundamentally limited to h/e². For comparative purposes, consider the drive current density within a Chern network, \({J}_{on}^{CN}={e}^{2}{V}_{on}/h{L}_{edge}\), with V_on being the drive voltage. Chern networks are currently incapable of approaching the current density in a CMOS transistor, \({J}_{on}^{CMOS}=874\,\mu A/\mu m\). However, additional iterations of Chern networks using different magnetic and/or topological materials may show increased current density by increasing the topological gap size, Δ_EX in the Chern network. Increases in Δ_EX effectively reduce the size of L_edge, thereby, increasing the resultant current density in a Chern network.

Nonetheless, the consequences of such low current flow within the device structure may best be understood by considering the device concepts of static and dynamic fan-out. Fan-out is defined as the number of logic-gate inputs that may be driven by the output of a given logic gate without degradation of the logical state. While the static—or resistive DC component—of fan-out may be improved by better mitigation of contact resistances in Chern networks, the dynamic—or AC capacitive component—is more pernicious. The speed at which a signal moves through logic gates is limited by the charging time of the inherent capacitance of the logic gates, leading to propagation delays. Propagation delays may be, in part, overcome by using higher input currents to charge the next logic gate, via

In Eq. (2), I_input is the input current fed into the logic element from a previous logic stage, C_logic is the capacitance and V_logic is the voltage of the current logic gate, respectively. Eq. (2) indicates that by increasing the current fed into subsequent logic stages from previous stages, the voltage across the current logic stage increases faster thereby increasing the speed of signal propagation. Cast in this light, the small output current from the Chern network will produce significant delays in signal propagation if integrated within a CMOS framework.

The advances put forth in the recent series of Chern network experiments represent a glimpse of the functionality and the variability of topological materials and responses. Given the difficulties discussed, namely scaling, temperature and performance, it is unlikely that such systems will find a home in next-generation CMOS technologies. However, while the specific expression of topological behavior may not impact the device architecture landscape, the important lessons learned within these impressive works must serve as the basis for continued exploration of topological materials from the applied or device perspective.

To me, the overarching question germane to both perspectives is “Does the presence of topology matter for enabling new technologies?". Nevertheless, many open questions remain from both the fundamental and applied perspectives. From the applied perspective, questions remain around fundamental device properties, such as understanding the electrostatic and transport properties of deposited metals on topological materials, as this relates directly to the device contact resistance—a crucial parameter in any application^15,29. From the fundamental perspective, an intriguing question surrounds the importance of crystallinity to device performance. Put another way: is it necessary to have perfectly crystalline topological materials to be able to exploit topological functionality? When considering time-reversal invariant topological materials, like (Bi,Sb)₂Se₃, the topological nature is protected by the inversion of band ordering that is brought about by the strength of the spin–orbit interaction. However, amorphous materials, characterized by randomized hopping strengths and positions of atoms within a material possessing neither long-range or short-range order, constructed from atoms with strong spin–orbit interactions, have been shown to possess the same topological features^30,31. Therefore, perhaps the consideration of a cheaper quasi-crystalline topological system may be able to produce similar behavior at lower cost and effort³², if the presence of a topological surface state is the critical requirement for device implementations.

Regardless, my perspective remains that the goal of topological technologies should be to replace functionality at the system level rather than at the level of individual devices. As we begin to look towards bringing the areas of condensed matter physics and device engineering closer, I believe that by starting the dialogue by examining some of the recent condensed matter successes and open device engineering questions to be addressed, we may collectively move towards a viable topological technology.

Authors and Affiliations

1. Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, 61801, USA

   Matthew J. Gilbert

Corresponding author

Correspondence to Matthew J. Gilbert.

Competing interests

The author declares no competing interests.

Peer review information

Nature Communications thanks the anonymous reviewers for their contribution to the peer review of this work.

Open Access This article is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License, which permits any non-commercial use, sharing, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if you modified the licensed material. You do not have permission under this licence to share adapted material derived from this article or parts of it. The images or other third party material in this article are included in the article’s Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by-nc-nd/4.0/.

Reprints and permissions